The invention relates to testing integrated circuits, and, more particularly, to a method and apparatus for isolating failure by precisely controlling the number of clocks applied during built-in self-test (BIST).
Built-in self-test (BIST) is used to test the memory arrays and logic circuits that are contained in high-end processors. BIST allows the memory arrays and logic circuits to be tested at and above system clock speeds using a locally generated pattern set that verifies functionality. Conceptually, the BIST approach is based on the realization that much of a circuit tester""s electronics is semiconductor-based, just like the products it is testing, and that many of the challenges and limitations in testing lie in the interface to the device under test (DUT). The BIST approach can be described as an attempt to move many of the already semiconductor-based test equipment functions into the products under test and eliminate the complex interfacing. One of the major advantages BIST has over other means of testing memory arrays is that the operation of the test is self-contained. All of the circuitry required to execute the test at-speed is contained within the integrated circuit. Very limited external controls are needed, so BIST can be run at all levels of packaging (wafer, TCA, module and system) without requiring expensive external test equipment.
BIST utilizes a boundary-scan design-for-test (DFT) technique. The DFT technique consists of placing a scannable memory element, or boundary-scan chain, adjacent to each integrated circuit I/O so that signals at the integrated circuit boundaries can be controlled and observed using scan operations and without direct contact with the integrated circuit. Access to the boundary-scan chain as well as to most of the DFT and BIST circuitry is through a custom five-wire interface similar to the standard IEEE 1149.1 TAP approach. This interface is used to initialize and control the various BIST controllers on the integrated circuits and other DFT hardware during both system test and manufacturing test. A state machine within each integrated circuit, referred to as the self-test control macro (STCM) is used to control internal-test-mode signals and the sequencing of all test and system clocks while in test mode. Instead of testing the performance of the device at full speed through the pins, an on-chip phase-locked loop (PLL) is used to multiply the incoming tester frequency to bring it up to the operating frequency of the integrated circuit. Additional self-generated clock (SGC) circuitry is then used to generate the various system clock sequences needed to properly exercise all portions of the integrated circuit. The BIST techniques can be divided into two major categories: logic BIST (LBIST) to test at-speed the logic in the devices, and array BIST (ABIST) to provide at-speed testing of the embedded arrays (i.e., RAMs).
Today, BIST engines are used to test logic and arrays by applying a large number of test patterns and compressing the results of these test patterns into a single signature. This signature is then compared to the one and only passing signature to determine if the logic or array that was tested is xe2x80x9cgoodxe2x80x9d. If the signature does not match the expected good signature, the logic or array is considered to have failed and thus have one or more defects. There is difficulty in diagnosing what defect is causing the failing signature. It is useful to determine what the failing defect is and whether there is any defect pattern that may indicate a weak design or processing sensitivity causing the failing signature, rather than just random defects.
This invention describes a method and apparatus, contained within an integrated circuit, for isolating failure by precisely controlling the number of clocks applied during built-in self-test (BIST). A programmable clock counter, on the integrated circuit, stores a specified number of clock cycles and sends a signal to stop the BIST once the specified number of clock cycles have been generated. The intermediate results can then be mapped at speed bit by bit in order to isolate the cause of failure.